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[Windows Develop] SDH

Description: 他是一个SDH上行代码，有八个模块组成的，能够传输以太网的数据 -He is an SDH uplink code, there is composed of eight modules, Ethernet can transmit data
Platform: | Size: 6144 | Author: 丁勇良 | Hits:

[Other] ethernet_controller

Description: 以太网控制器MAC的verilog代码，已经过验证，可以用。-Ethernet Controller
Platform: | Size: 90112 | Author: 李阳 | Hits:

[VHDL-FPGA-Verilog] ldpc_encoder_802_3an_latest.tar

Description: 适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。-LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
Platform: | Size: 620544 | Author: liang | Hits:

[VHDL-FPGA-Verilog] MACtop

Description: 基于FPGA的以太网控制器（MAC）源码，包括发送、接收、控制、CRC、寄存器、计数器等模块-Ethernet MAC sub-layer protocol
Platform: | Size: 128000 | Author: cmf | Hits:

[VHDL-FPGA-Verilog] ethernet10-100M-IP-core

Description: 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
Platform: | Size: 740352 | Author: owen | Hits:

[VHDL-FPGA-Verilog] 101259356ethernet

Description: etherent testbeanch by using verilog hdl
Platform: | Size: 1016832 | Author: weike | Hits:

[VHDL-FPGA-Verilog] ethernet(MAC)verilog-langue

Description: 用veriolog编写以太网控制器（ＭＡＣ）-ｅｔｈｅｒｎｅｔ MAC of verilog
Platform: | Size: 138240 | Author: 刘大 | Hits:

[TCP/IP stack] MAC_verilog

Description: 以太网MAC网卡的Verilog源代码，可以节省TCP/IP协议的设计开发时间。-Verilog source code for Ethernet MAC network card, you can save the TCP/IP protocol design and development time.
Platform: | Size: 125952 | Author: lxk | Hits:

[VHDL-FPGA-Verilog] MII

Description: 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
Platform: | Size: 2048 | Author: 雷伟林 | Hits:

[VHDL-FPGA-Verilog] verilog-ip-core

Description: verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
Platform: | Size: 3798016 | Author: 刘兵 | Hits:

[VHDL-FPGA-Verilog] EtherNet

Description: 以太网控制器的FPGA实现,用Verilog语言编写!-Ethernet controller FPGA, Verilog language!
Platform: | Size: 142336 | Author: Shawn | Hits:

[VHDL-FPGA-Verilog] ethernet-verilog

Description: 非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考-Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference
Platform: | Size: 704512 | Author: 瞿鑫 | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: verilog写的以太网硬件模型，使用xilinx FPGA，ieee802.3ae-an ethernet model in Verilog，using a Xilinx FPGA，and the function：IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation
Platform: | Size: 788480 | Author: AricSnow | Hits:

[Other] Three-speed-Ethernet-Verilog-source

Description: Verilog的三速以太网源程序，文件中包含源程序和测试程序.-Three-speed Ethernet Verilog source
Platform: | Size: 130048 | Author: pang | Hits:

[Other] verilog-ethernet-master

Description: sivasankar is a good boy,,, njknsdjnjkgnjskn sjnkdnsgkjndjks jdskgnskdndgksj ksnklgnkl
Platform: | Size: 943104 | Author: sankula sivasankar | Hits:

[VHDL-FPGA-Verilog] 10_100M-Ethernet-

Description: 10M 100M 以太网 Verilog 源代码-10M 100M Ethernet
Platform: | Size: 89088 | Author: horacedu | Hits:

[VHDL-FPGA-Verilog] ethernet

Description: opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。-Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim.
Platform: | Size: 1017856 | Author: TSH | Hits:

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[Windows Develop] SDH

[Other] ethernet_controller

[VHDL-FPGA-Verilog] ldpc_encoder_802_3an_latest.tar

[VHDL-FPGA-Verilog] MACtop

[VHDL-FPGA-Verilog] ethernet10-100M-IP-core

[VHDL-FPGA-Verilog] 101259356ethernet

[VHDL-FPGA-Verilog] ethernet(MAC)verilog-langue

[TCP/IP stack] MAC_verilog

[VHDL-FPGA-Verilog] MII

[VHDL-FPGA-Verilog] verilog-ip-core

[VHDL-FPGA-Verilog] EtherNet

[VHDL-FPGA-Verilog] ethernet-verilog

[VHDL-FPGA-Verilog] ethernet.tar

[Other] Three-speed-Ethernet-Verilog-source

[Other] verilog-ethernet-master

[VHDL-FPGA-Verilog] 10_100M-Ethernet-

[VHDL-FPGA-Verilog] ethernet

[VHDL-FPGA-Verilog] ethernet

[Internet-Network] CH03_RGMII_UDP_TEST

[VHDL-FPGA-Verilog] W5300_IF

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